Skip to content
Projects
Groups
Snippets
Help
This project
Loading...
Sign in / Register
Toggle navigation
C
cwe_checker
Overview
Overview
Details
Activity
Cycle Analytics
Repository
Repository
Files
Commits
Branches
Tags
Contributors
Graph
Compare
Charts
Issues
0
Issues
0
List
Board
Labels
Milestones
Merge Requests
0
Merge Requests
0
CI / CD
CI / CD
Pipelines
Jobs
Schedules
Charts
Wiki
Wiki
Snippets
Snippets
Members
Members
Collapse sidebar
Close sidebar
Activity
Graph
Charts
Create a new issue
Jobs
Commits
Issue Boards
Open sidebar
fact-depend
cwe_checker
Commits
08aa5544
Unverified
Commit
08aa5544
authored
Apr 28, 2021
by
Enkelmann
Committed by
GitHub
Apr 28, 2021
Browse files
Options
Browse Files
Download
Email Patches
Plain Diff
Fix bug in sub register handling (#172)
parent
44a194f7
Hide whitespace changes
Inline
Side-by-side
Showing
3 changed files
with
37 additions
and
7 deletions
+37
-7
expression.rs
...checker_lib/src/intermediate_representation/expression.rs
+16
-5
tests.rs
...r_lib/src/intermediate_representation/expression/tests.rs
+20
-0
HelperFunctions.java
src/ghidra/p_code_extractor/internal/HelperFunctions.java
+1
-2
No files found.
src/cwe_checker_lib/src/intermediate_representation/expression.rs
View file @
08aa5544
...
...
@@ -368,8 +368,20 @@ impl Expression {
is_temp
:
false
,
}));
// Build PIECE as PIECE(lhs:PIECE(lhs:higher subpiece, rhs:sub register), rhs:lower subpiece)
if
sub_register
.lsb
>
ByteSize
::
new
(
0
)
{
if
sub_register
.lsb
>
ByteSize
::
new
(
0
)
&&
sub_register
.lsb
+
sub_register
.size
==
base_size
{
// Build PIECE as PIECE(lhs: sub_register, rhs: low subpiece)
*
self
=
Expression
::
BinOp
{
op
:
BinOpType
::
Piece
,
lhs
:
Box
::
new
(
self
.clone
()),
rhs
:
Box
::
new
(
Expression
::
Subpiece
{
low_byte
:
ByteSize
::
new
(
0
),
size
:
sub_lsb
,
arg
:
base_subpiece
,
}),
}
}
else
if
sub_register
.lsb
>
ByteSize
::
new
(
0
)
{
// Build PIECE as PIECE(lhs:PIECE(lhs:higher subpiece, rhs:sub register), rhs:lower subpiece)
*
self
=
Expression
::
BinOp
{
op
:
BinOpType
::
Piece
,
lhs
:
Box
::
new
(
Expression
::
BinOp
{
...
...
@@ -387,9 +399,8 @@ impl Expression {
arg
:
base_subpiece
,
}),
}
}
// Build PIECE as PIECE(lhs: high subpiece, rhs: sub register)
else
{
}
else
{
// Build PIECE as PIECE(lhs: high subpiece, rhs: sub register)
*
self
=
Expression
::
BinOp
{
op
:
BinOpType
::
Piece
,
lhs
:
Box
::
new
(
Expression
::
Subpiece
{
...
...
src/cwe_checker_lib/src/intermediate_representation/expression/tests.rs
View file @
08aa5544
...
...
@@ -208,6 +208,26 @@ fn piecing_expressions_together() {
.piece_two_expressions_together
(
&
setup
.rax_register
,
&
setup
.higher_byte_register
);
assert_eq!
(
expr
,
expected_expr
);
assert_eq!
(
higher_byte_exp
,
expected_higher_byte_expr
);
let
higher_half_rax
=
RegisterProperties
{
register
:
"upper_RAX_half"
.to_string
(),
base_register
:
"RAX"
.to_string
(),
lsb
:
ByteSize
::
new
(
4
),
size
:
ByteSize
::
new
(
4
),
};
let
mut
expression
=
Expression
::
Const
(
Bitvector
::
from_u32
(
42
));
let
expected_output
=
Expression
::
BinOp
{
op
:
BinOpType
::
Piece
,
lhs
:
Box
::
new
(
expression
.clone
()),
rhs
:
Box
::
new
(
Expression
::
Subpiece
{
low_byte
:
ByteSize
(
0
),
size
:
ByteSize
::
new
(
4
),
arg
:
Box
::
new
(
setup
.rax_variable
.clone
()),
}),
};
expression
.piece_two_expressions_together
(
&
setup
.rax_register
,
&
higher_half_rax
);
assert_eq!
(
expression
,
expected_output
);
}
#[test]
...
...
src/ghidra/p_code_extractor/internal/HelperFunctions.java
View file @
08aa5544
...
...
@@ -235,12 +235,11 @@ public final class HelperFunctions {
public
static
ArrayList
<
RegisterProperties
>
getRegisterList
()
{
ArrayList
<
RegisterProperties
>
regProps
=
new
ArrayList
<
RegisterProperties
>();
Language
language
=
ghidraProgram
.
getLanguage
();
int
archSizeInBytes
=
(
int
)(
language
.
getLanguageDescription
().
getSize
()
/
8
);
for
(
Register
reg
:
language
.
getRegisters
())
{
regProps
.
add
(
new
RegisterProperties
(
reg
.
getName
(),
reg
.
getBaseRegister
().
getName
(),
(
int
)(
reg
.
getLeastSignificatBitInBaseRegister
()
/
archSizeInBytes
),
(
int
)(
reg
.
getLeastSignificatBitInBaseRegister
()
/
8
),
context
.
getRegisterVarnode
(
reg
).
getSize
())
);
}
...
...
Write
Preview
Markdown
is supported
0%
Try again
or
attach a new file
Attach a file
Cancel
You are about to add
0
people
to the discussion. Proceed with caution.
Finish editing this message first!
Cancel
Please
register
or
sign in
to comment