Commit b4398642 by Joseph Pantoga

Xilinx FPGA bitstream

parent eeaf9ce5
...@@ -79,3 +79,7 @@ ...@@ -79,3 +79,7 @@
0 string \x00\x53\x46\x48 OSX DMG image 0 string \x00\x53\x46\x48 OSX DMG image
>0x38 string !d\x00i\x00s\x00k\x00\x20\x00i\x00m\x00a\x00g\x00e invalid{invalid) >0x38 string !d\x00i\x00s\x00k\x00\x20\x00i\x00m\x00a\x00g\x00e invalid{invalid)
# Xilinx FPGA Bitstream
# Ref: http://www.xilinx.com/support/answers/7891.html
0 ubequad 0xffffffffaa995566 Xilinx Virtex/Spartan FPGA bitstream dummy + sync word
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